Dynamic Leakage-Energy Management of Secondary Caches

Static leakage currents are the prime contributor to energy consumption for large on-chip secondary/tertiary caches. This energy cost can be reduced by dynamically disabling unneeded portions of the cache. To provide overall energy savings, however, the leakage-energy reduction must exceed the extra energy incurred due to additional off-chip accesses and increased runtime. We derive a practical formula for on-line estimation of net energy reduction based on the number of additional misses incurred and the ratio of off-chip access energy to per-cycle cache leakage energy. We estimate reasonable values for this ratio by measuring the actual off-chip access energy cost on a current system. We incorporate our estimation formula into a previously proposed dynamic resizing scheme, preventing it from increasing net energy consumption and improving its overall effectiveness. We also present a new resizing framework that tracks misses and controls power at the granularity of associative ways. Per-way miss counters enable simultaneous estimation of net energy consumption at all possible cache sizes, allowing direct identification of the minimum-energy configuration. This structure also greatly reduces hardware overhead compared to block-level resizing schemes. We call the combination of this framework with our estimation formula Energy Aware Bank-Level Resizing (EnABLR). Simulations show that, across the entire SPEC CPU2000 suite, EnABLR reduces secondary-cache leakage energy by up to 80%, without increasing overall memory-system energy consumption by more than 1% in any situation. Average energy reductions range 14% to 29%, depending on off-chip access energy costs.